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Data Sheet March 1999
T7504 and T5504 Quad PCM Codecs with Filters
Features
s s
s s
Operating temperature range: -40 C to +85 C -law/A-law companding selectable
5 V only Low-power, latch-up-free CMOS technology -- 37 mW/channel typical operating power dissipation -- 1 mW/channel typical powerdown dissipation Automatic master clock frequency selection -- 2.048 MHz or 4.096 MHz On-chip sample and hold, autozero, and precision voltage reference Differential architecture for high noise immunity and power supply rejection Flexible time-slotted PCM interface -- 2.048 MHz or 4.096 MHz data rate Meets or exceeds ITU-T G.711--G.714 requirements and VF characteristics of D3/D4 (as per Lucent Technologies PUB43801)
Description
The T7504 and T5504 devices are single-chip, fourchannel -law/A-law PCM codecs with filters. These integrated circuits provide analog-to-digital and digital-to-analog conversion. They provide the transmit and receive filtering necessary to interface a voice telephone circuit to a time-division multiplexed system. These devices are available in 28-pin PLCCs. The T7504 is also available in a 44-pin MQFP. The T5504 differs from the T7504 in its timing mode. The T5504 operates in the nondelay timing mode (digital data valid when frame sync goes high), and the T7504 operates in the delayed timing mode (digital data is valid one clock cycle after frame sync goes high) (see Figures 6--9).
s
s
s
s
s
GSX0 VFXIN0 - + +2.4 V FILTER NETWORK
DX DR ENCODER PCM INTERFACE FSX0 FSX1 FSX2 FSX3 FSEP GNDD
CHANNEL 0
VFRO0
FILTER NETWORK
DECODER
POWERDOWN CONTROL INTERNAL TIMING & CONTROL MCLK ASEL VDD (2)
GSX1 VFXINF1 VFRO1 GSX2 VFXIN2 VFRO2 GSX3 VFXIN3 VFRO3
CHANNEL 1
CHANNEL 2
CHANNEL 3
BIAS CIRCUITRY & REFERENCE
VDD (2) (MQFP ONLY) GNDA (4) (PLCC ONLY) GNDA (5) (MQFP ONLY)
5-3579.d(C)
Figure 1. Block Diagram For 28-Pin DIP and 28-Pin PLCC
T7504 and T5504 Quad PCM Codecs with Filters
Data Sheet March 1999
Functional Description
Four channels of PCM data input and output are passed through only two ports, DX and DR, so some type of time-slot assignment is necessary. The scheme used here is to utilize timing modes of 32 or 64 time slots corresponding to master clock frequencies of either 2.048 MHz or 4.096 MHz, respectively. Each device has four transmit frame sync (FSX) inputs, one for each channel. During a single 125 s frame, each transmit frame sync input is supplied a single pulse. The timing of the pulse indicates the beginning of the time slot during which the data for that channel is clocked out of the device. During a frame, transmit frame sync pulses must be separated from each other by one or more time slots. A channel is placed in a standby (low-power) mode if its FSX input has been low for 500 s. There is a single frame sync separation input (FSEP). The number of negative clock edges minus one that occurs while FSEP is high is the delay (in clock periods) that is placed between the rising edge of a transmit frame sign bit and the falling edge used by the receiver to sample the sign bit. There must always be a pulse on the FSEP input since this input provides the 8 kHz signal required to maintain internal timing. If the FSEP pulse is one clock period or less, the device makes the transmit edges and receive sampling edges one half clock period apart. The entire device is placed in a powerdown mode if FSEP remains low for 500 s. Time slot zero is defined as starting on the first rising MCLK edge after FSEP = 1 is detected by a negative MCLK edge. In the T7504, MCLK negative-going edges that detect the start of FSEP and FSXN must be integer multiples of eight MCLK periods apart (zero multiples are allowed). Since FSEP is assumed to define time slot 0, the number of multiples separating FSXN and FSEP is the time-slot number. In the T5504, FSXN for time slot 0 nominally starts on the MCLK positive edge following the negative edge which detects FSEP.
The frequency of the master clock must be either 2.048 MHz or 4.096 MHz. Internal circuitry determines the master clock frequency during the powerup reset interval. Powerdown is not guaranteed if MCLK is lost unless the device is already in the powerdown mode due to FSEP low for at least 500 s. The analog input section in Figure 2 includes an onchip op amp that is used in conjunction with external, user-supplied resistors to vary encoder passband gain. The feedback resistance (RF) should range from 10 k to 200 k and capacitance from GSx to ground should be kept to less than 50 pF. The input signal at VFXIN should be ac coupled. For best performance, the maximum gain of this op amp should be limited to 20 dB or less.
RF GSX
RI
VFXIN - + 2.4 V GAIN = RX RI
5-3786
TO CODEC FILTERS
Figure 2. Typical Analog Input Section
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Lucent Technologies Inc.
Data Sheet March 1999
T7504 and T5504 Quad PCM Codecs with Filters
Pin Information
GNDD FSEP DR DX FSX3 FSX2 27 FSX1 26
3
4
2
1
MCLK ASEL VDD VFXIN2 GSX2 VFRO2 GNDA2
5 6 7 8 9 10 11
28
25 24 23
FSX0 VDD GNDA0 VFXIN0 GSX0 VFRO0 GNDA1
T - 7504 - - - ML T - 5504 - - - ML
22 21 20 19
12
13
14
15
16
17 GSX1
VFXIN3
GNDA3
VFXIN1
VFRO3
VFRO1
GSX3
18
5-3580.b
Figure 3. 28-Pin PLCC Pin Diagram
GNDD
FSEP
DR
41
39
44
43
42
40
38
37
36
FSX3
35
FSX2
MCLK ASEL VDD VDDA NC NC NC VFXIN2 GSX2 VFRO2 GNDA2
1 2 3 4 5 6 7 8 9 10 11
20 12 13 14 15 16 17 18 19 21 22
34
FSX1
NC
NC
NC
NC
DX
33 32 31 30 29 T7504---JL 28 27 26 25 24 23
FSX0 NC VDD VDDA NC NC GNDA0 VFXIN0 GS X0 VFRO0 GNDA1
VFRO3
VFXIN3
VFXIN1
GNDA3
GNDA4
VFRO1
NC
NC
GSX3
GSX1
NC
5-4770
Figure 4. 44-Pin MQFP Pin Diagram
Lucent Technologies Inc.
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T7504 and T5504 Quad PCM Codecs with Filters
Data Sheet March 1999
Pin Information (continued)
Table 1. Pin Descriptions
Pin Symbol PLCC MQFP VFXIN3 VFXIN2 VFXIN1 VFXIN0 GSX3 GSX2 GSX1 GSX0 VFRO3 VFRO2 VFRO1 VFRO0 VDD [1:0] VDDA [1:0] 14 8 16 22 13 9 17 21 12 10 18 20 7, 24 -- 15 8 19 26 14 9 20 25 13 10 21 24 3, 31 4, 30 I Voice Frequency Transmitter Input. Analog inverting input to the uncommitted operational amplifier at the transmit filter input. Connect the signal to be digitized to this pin through a resistor RI (see Figure 2). Gain Set for Transmitter. Output of the transmit uncommitted operational amplifier. The pin is the input to the transmit differential filters. Connect the pin to its corresponding VFXIN through a resistor RF (see Figure 2). Voice Frequency Receiver Output. This pin can drive 2000 (or greater) loads. Type* Name/Function
O
O
--
GNDA4 GNDA3 GNDA2 GNDA1 GNDA0 DR
-- 15 11 19 23 4
18 16 11 23 27 44
--
5 V Digital and Analog Power Supplies. All pins must be connected on the circuit board. Each pin should be bypassed to ground with at least 0.1 F of capacitance as close to the device as possible. For the DIP and PLCC packages, VDD serves both analog and digital internal circuits. Analog Grounds. All ground pins must be connected on the circuit board.
I
DX
3
43
O
MCLK
5
1
I
GNDD FSX3 FSX2 FSX1 FSX0
2 28 27 26 25
41 36 35 34 33
-- Id
ASEL FSEP
6 1
2 37
Id I
Receive PCM Data Input. The data on this pin is shifted into the device on the falling edges of MCLK. Data is only entered for valid time slots as defined by the relationship of the pulses on the FSX inputs and the pulse on the FSEP input. Transmit PCM Data Output. This pin remains in the high-impedance state except during active transmit time slots. An active transmit time slot is defined as one in which a pulse is present on one of the FSx inputs. Data is shifted out on the rising edge of MCLK. Master Clock Input. The frequency must be 2.048 MHz or 4.096 MHz. This clock serves as the bit clock for all PCM data transfer. A 40% to 60% duty cycle is required. Digital Ground. Ground connection for the digital circuitry. All ground pins must be connected on the circuit board. Transmit Frame Sync. This signal is an edge trigger and must be high for a minimum of one MCLK cycle. This signal must be derived from MCLK. The division ratio is 1:256 or 1:512 (FSX:MCLK). Each FSX input must have a pulse present at the start of the desired active output time slot. Pulses on the various FSX inputs must be separated by one or more integer multiples of time slots. An internal pull-down device is included on each FSX. A-Law/-Law Select. A logic low selects -law coding. A logic high selects A-law coding. A pull-down device is included. Frame Sync Separation. The pulse width of this 8 kHz signal defines the timing offset between the transmit and receive frames. Internally generated receive frame sync pulses are delayed from the corresponding transmit frame sync pulse rising edge by one less than the FSEP pulse width in negative MCLK edges. If the pulse width is one MCLK period or less, the transmit and receive frame syncs are made coincident. Loss of FSEP causes the device to powerdown. If the master clock frequency is 2.048 MHz or 4.096 MHz, delays of 255 or 511 clock pulses are not allowed, respectively. Timing relationships between FSEP, FSXN, and time slot 0 are given in Figures 6--9.
* Id Indicates a pull-down device is included on this lead.
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Lucent Technologies Inc.
Data Sheet March 1999
T7504 and T5504 Quad PCM Codecs with Filters
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Storage Temperature Range Power Supply Voltage Voltage on Any Pin with Respect to Ground Maximum Power Dissipation (package limit) Symbol Tstg VDD -- PD Min -55 -- -0.5 -- Max 150 6.5 0.5 + VDD 600 Unit C V V mW
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent Technologies Microelectronics Group employs a human-body model (HBM) and a charged-device model (CDM) for ESD susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance = 1500 , capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters: HBM ESD Threshold Voltage Device Rating T7504 >2000 V T5504 >2000 V
Electrical Characteristics
Specifications apply for TA = -40 C to +85 C, VDD = 5 V 5%, MCLK = either 2.048 MHz or 4.096 MHz, and GND = 0 V, unless otherwise noted.
dc Characteristics
Table 2. Digital Interface Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Current, Pins without Pull-down Input Current, Pins with Pull-down Output Current in High-impedance State Input Capacitance Symbol VIL VIH VOL VOH II II IOZ CI Test Conditions All digital inputs All digital inputs DX, IL = 3.2 mA DX, IL = -3.2 mA DX, IL = -320 A Any digital input GND < VIN < VDD Any digital input GND < VIN < VDD DX -- Min -- 2.0 -- 2.4 3.5 -10 -- -30 -- Typ Max -- 0.8 -- -- -- 0.4 -- -- -- -- -- 10 -- -- -- 150 30 5 Unit V V V V V A A A pF
Lucent Technologies Inc.
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T7504 and T5504 Quad PCM Codecs with Filters
Data Sheet March 1999
Electrical Characteristics (continued)
Table 3. Power Dissipation Power measurements are made at MCLK = 4.096 MHz, outputs unloaded. Parameter Powerdown Current Powerup Current Standby Current Symbol IDD0 IDD1 IDDS Test Conditions MCLK present, FSX[3:0] = 0.4 V, FSEP = 0.4 V MCLK, FSX[3:0], FSEP present MCLK, FSEP present; FSX[3:0] = 0.4 V Min -- -- -- Typ 0.2 30 6 Max 1 40 10 Unit mA mA mA
Transmission Characteristics
Table 4. Analog Interface Parameter Input Resistance, VFXIN Input Leakage Current, VFXIN dc Open-loop Voltage Gain, GSX Open-loop Unity Gain Bandwidth, GSX Load Capacitance, GSX Load Resistance, GSX Input Voltage, VFXIN Load Resistance, VFRO Load Capacitance, VFRO Output Resistance, VFRO Symbol RVFXI IBVFXI AVOL fO CLX1 RLX1 VIX RLVFRO CLVFRO ROVFRO Test Conditions 0.25 V < VFxI < 4.75 V 0.25 V < VFxI < 4.75 V -- -- -- -- Relative to ground -- -- 0 dBm0, 1020 Hz PCM code applied to DR Partial powerdown FSX = 0 for channel under test Alternating zero -law PCM code applied to DR FSX[3:0] = 0.4 V, FSEP = active, no load FSEP = 0.4 V RL = 2000 Min Typ 1.0 -- -- -- 5000 -- 1 3 -- -- 10 -- 2.25 2.35 2000 -- -- -- -- -- 3000 -- Max -- 2.4 -- -- 50 -- 2.5 -- 100 20 10000 2.5 2.65 30 -- Unit M A -- MHz pF k V pF V V A Vp-p
Output Voltage, VFRO Output Voltage, VFRO, Standby Output Leakage Current, VFRO, Powerdown Output Voltage Swing, VFRO
VOR VORPD IOVFRO VSWR
2.25 2.35 2.15 -30 3.2 2.4 -- --
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Lucent Technologies Inc.
Data Sheet March 1999
T7504 and T5504 Quad PCM Codecs with Filters
Transmission Characteristics (continued)
ac Transmission Characteristics
Unless otherwise noted, the analog input is a 0 dBm0, 1020 Hz sine wave; the input amplifier is set for unity gain. The digital input is a PCM bit stream equivalent to that obtained by passing a 0 dBm0, 1020 Hz sine wave through an ideal encoder. The output level is sin(x)/x-corrected. Table 5. Absolute Gain Parameter Symbol Test Conditions Encoder Milliwatt EmW Signal input of 0.775 Vrms, -law or Response (transmit gain tolerA-law ance) Decoder Milliwatt DmW Measured relative to 0.775 Vrms -law Response (receive gain toleror A-law, ance) PCM input of 0 dBm0 1020 Hz RL = 10 k Table 6. Gain Tracking Parameter Transmit Gain Tracking Error Sinusoidal Input -Law/A-Law Receive Gain Tracking Error Sinusoidal Input -Law/A-Law Table 7. Distortion Parameter Transmit Signal to Distortion Symbol SDX Test Conditions -law 3 dBm0 VFXI -30 dBm0 A-law 3 dBm0 VFXI -30 dBm0 -law -30 dBm0 VFXI -40 dBm0 A-law -30 dBm0 VFXI -40 dBm0 -law -40 dBm0 VFxI -45 dBm0 A-law -40 dBm0 VFxI -45 dBm0 -law 3 dBm0 VFRO -30 dBm0 A-law 3 dBm0 VFRO -30 dBm0 -law -30 dBm0 VFRO -40 dBm0 A-law -30 dBm0 VFRO -40 dBm0 -law -40 dBm0 VFRO -45 dBm0 A-law -40 dBm0 VFRO -45 dBm0 200 Hz--3400 Hz, 0 dBm0 input, output any other single frequency 3400 Hz 200 Hz--3400 Hz, 0 dBm0 input, output any other single frequency 3400 Hz Transmit or receive, two frequencies in the range (300 Hz--3400 Hz) at -6 dBm0 Min 36 35 30 29 25 25 36 35 30 29 25 25 -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max Unit -- dB -- dB -- dB -- dB -- dB -- dB -- dB -- dB -- dB -- dB -- dB -- dB -38 dBm0 Symbol GTX GTR Test Conditions +3 dBm0 to -37 dBm0 -37 dBm0 to -50 dBm0 +3 dBm0 to -37 dBm0 -37 dBm0 to -50 dBm0 Min -0.25 -0.50 -0.25 -0.50 Typ -- -- -- -- Max 0.25 0.50 0.25 0.50 Unit dB dB dB dB Min -0.25 Typ -- Max 0.25 Unit dBm0
-0.25
--
0.25
dBm0
Receive Signal to Distortion
SDR
Single Frequency Distortion, Transmit Single Frequency Distortion, Receive Intermodulation Distortion
SFDX
SFDR
--
--
-40
dBm0
IMD
--
--
-42
dBm0
Lucent Technologies Inc.
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T7504 and T5504 Quad PCM Codecs with Filters
Data Sheet March 1999
Transmission Characteristics (continued)
Table 8. Envelope Delay Distortion Parameter TX Delay, Absolute* TX Delay, Relative to 1600 Hz Symbol DXA DXR Test Conditions f = 1600 Hz f = 500 Hz--600 Hz f = 600 Hz--800 Hz f = 800 Hz--1000 Hz f = 1000 Hz--1600 Hz f = 1600 Hz--2600 Hz f = 2600 Hz--2800 Hz f = 2800 Hz--3000 Hz f = 1600 Hz f = 500 Hz--1000 Hz f = 1000 Hz--1600 Hz f = 1600 Hz--2600 Hz f = 2600 Hz--2800 Hz f = 2800 Hz--3000 Hz Any time slot/channel to any time slot/channel f = 1600 Hz Min -- -- -- -- -- -- -- -- -- -40 -30 -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 175 to 425 220 145 75 40 75 105 155 150 to 405 -- -- 90 125 175 325 to 650 Unit s s s s s s s s s s s s s s s
RX Delay, Absolute* RX Delay, Relative to 1600 Hz
DRA DRR
Round Trip Delay, Absolute*
DRTA
* Varies as a function of time slots chosen.
Overload Compression Figure 5 shows the region of operation for encoder signal levels above the reference input power (0 dBm0).
9 8
FUNDAMENTAL OUTPUT POWER (dBm)
7
6
5 ACCEPTABLE REGION 4
3
2
1
1
2
3
4
5
6
7
8
9
FUNDAMENTAL INPUT POWER (dBm)
5-3586
Figure 5. Overload Compression 8 Lucent Technologies Inc.
Data Sheet March 1999
T7504 and T5504 Quad PCM Codecs with Filters
Transmission Characteristics (continued)
Table 9. Noise Parameter Transmit Noise -Law Transmit Noise A-Law Receive Noise -Law Receive Noise A-Law Noise, Single Frequency f = 0 kHz--100 kHz Power Supply Rejection Transmit Symbol NXC NXP NRC NRP NRS PSRX Test Conditions -- Input amplifier gain = 20 dB -- PCM code is alternating positive and negative zero PCM code is A-law positive one VFXIN = 0 Vrms, measurement at VFRO, DR = DX VDD = 5.0 Vdc + 100 mVrms: f = 0 kHz--4 kHz f = 4 kHz--50 kHz PCM code is positive one LSB VDD = 5.0 Vdc + 100 mVrms: f = 0 kHz--4 kHz f = 4 kHz--25 kHz f = 25 kHz--50 kHz 0 dBm0, 300 Hz--3400 Hz input PCM code applied: 4600 Hz--7600 Hz 7600 Hz--8400 Hz 8400 Hz--50 kHz Min -- -- -- -- -- -- Typ -- -- -- -- -- -- Max 18 19 -68 13 -75 -53 Unit dBrnC0 dBrnC0 dBm0p dBrnC0 dBm0p dBm0
36 30
-- --
-- --
dB dB
Power Supply Rejection Receive
PSRX
36 40 30
-- -- --
-- -- --
dB dB dB
Spurious Out-of-Band Signals at VFRO Relative to Input
SOS
-- -- --
-- -- --
-30 -40 -30
dB dB dB
Table 10. Receive Gain Relative to Gain at 1.02 kHz Frequency (Hz) Below 3000 3140 3380 3860 4600 and above Min -0.150 -0.570 -0.885 -- -- Typ 0.04 0.04 -0.58 -10.7 -- Max 0.150 0.150 0.010 -9.4 -28 Unit dB dB dB dB dB
Table 11. Transmit Gain Relative to Gain at 1.02 kHz Frequency (Hz) 16.67 40 50 60 200 300 to 3000 3140 3380 3860 4600 and above Min -- -- -- -- -1.8 -0.150 -0.570 -0.885 -- -- Typ -50 -34 -36 -50 -0.5 0.04 0.04 -0.58 -10.7 -- Max -30 -26 -30 -30 0 0.150 0.150 0.010 -9.4 -32 Unit dB dB dB dB dB dB dB dB dB dB
Lucent Technologies Inc.
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T7504 and T5504 Quad PCM Codecs with Filters
Data Sheet March 1999
Transmission Characteristics (continued)
Table 12. Interchannel Crosstalk (Between Channels) RF = 200 k (See note below.) Parameter Transmit to Receive Crosstalk 0 dBm0 Transmit Levels Receive to Transmit Crosstalk 0 dBm0 Receive Levels Transmit to Transmit Crosstalk 0 dBm0 Transmit Levels Receive to Receive Crosstalk 0 dBm0 Receive Levels Test Conditions f = 300 Hz--3400 Hz idle PCM code for channel under test; 0 dBm0 into any other single channel VFXIN CTRX-XY f = 300 Hz--3400 Hz VFXIN = 0 Vrms for channel under test; 0 dBm0 code level on any other single channel DR CTXX-XY f = 300 Hz--3400 Hz 0 dBm0 applied to any single channel VFXIN except channel under test, which has VFXIN = 0 Vrms CTRX-RY f = 300 Hz--3400 Hz 0 dBm0 code level on any single channel DR except channel under test, which has idle code applied Symbol CTXX-RY Min -- Typ -95 Max -75 Unit dB
--
-92
-75
dB
--
-90
-75
dB
--
-95
-75
dB
Table 13. Intrachannel Crosstalk (Within Channels) RF = 200 k (See Note below.) Parameter Symbol Transmit to Receive CTXX-RX Crosstalk 0 dBm0 Transmit Levels Receive to Transmit CTRX-XX Crosstalk 0 dBm0 Receive Levels Test Conditions f = 300 Hz--3400 Hz idle PCM code for channel under test; 0 dBm0 into VFXIN f = 300 Hz--3400 Hz VFXIN = 0 Vrms for channel under test; 0 dBm0 code level on DR Min -- Typ -95 Max -65 Unit dB
--
-73
-65
dB
Note: For Tables 11 and 12, crosstalk into the transmit channels (VFXIN) can be significantly affected by parasitic capacitive feeds from GSX and VFRO outputs. PWB layouts should be arranged to keep these parasitics low. The resistor value of RF (from GSX to VFXIN) should also be kept as low as possible (while maintaining the load on GSX above 10 k per Table 4) to minimize crosstalk.
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Lucent Technologies Inc.
Data Sheet March 1999
T7504 and T5504 Quad PCM Codecs with Filters
Timing Characteristics
Table 14. Clock Section (See Figures 6, 7, 8, and 9.) Symbol tMCHMCL1 tCDC tMCH1MCH2 tMCL2MCL1 Parameter Clock Pulse Width Duty Cycle, MC Clock Rise and Fall Time Test Conditions -- -- -- Min 97 40 0 Typ -- -- -- Max -- 60 15 Unit ns % ns
Table 15. T7504 Transmit Section (See Figure 6.) Symbol tMCHDV tMCHDV1 tMCLDZ* tFSHMCL tMCLFSH tFSLMCL tFSHFSL Parameter Data Enabled on TS Entry Data Delay from MC Data Float on TS Exit Frame-sync Hold Time Frame-sync High Setup Frame-sync Low Setup Frame-sync Pulse Width Test Conditions 0 < CLOAD < 100 pF 0 < CLOAD < 100 pF CLOAD = 0 -- -- -- -- Min 0 0 15 50 50 50 0.1 Typ -- -- -- -- -- -- -- Max 60 60 100 -- -- -- 125 - tMCHMCH Unit ns ns ns ns ns ns s
* Timing parameter tMCLDZ is referenced to a high-impedance state.
Table 16. T5504 Transmit Section (See Figure 8.) Symbol tFSHDV tMCHDV1 tMCHDZ* tFSHMCL tMCLFSH tFSLMCL tFSHFSL Parameter Data Enabled on TS Entry Data Delay from FSX Data Float on TS Exit Frame-sync Hold Time Frame-sync High Setup Frame-sync Low Setup Frame-sync Pulse Width Test Conditions 0 < CLOAD < 100 pF 0 < CLOAD < 100 pF CLOAD = 0 -- -- -- -- Min 0 0 0 50 50 50 0.1 Typ -- -- -- -- -- -- -- Max 80 60 30 -- -- -- 125 - tMCHMCH Unit ns ns ns ns ns ns s
* Timing parameter tMCHDZ is referenced to a high-impedance state.
Lucent Technologies Inc.
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T7504 and T5504 Quad PCM Codecs with Filters
Data Sheet March 1999
Timing Characteristics (continued)
Table 17. T7504 and T5504 Receive Section (See Figures 6, 7, 8, and 9.) Symbol tDVMCL tMCLDV tSPHMCL tMCLSPH tSPLMCL Parameter Receive Data Setup Receive Data Hold Frame Separation Hold Time Frame Separation High Setup Frame Separation Low Setup Test Conditions -- -- -- -- --
TIME SLOT tMCHMCL1 MCLK tMCLFSH tFSHMCL FSxN FSHFSL tMCHDV Dx tMCLSPH FSEP BIT 1 tMCHDV1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 tMCLDZ BIT 7 BIT 8
Min 30 15 50 50 50
Typ -- -- -- -- --
Max -- -- -- -- --
Unit ns ns ns ns ns
1
2 tMCH1MCH2 tFSLMCL
3
4
5 tMCL2MCL1
6 tFSLMCL
7
8
1
tDVMCL DR BIT 1 BIT 2 DR STABLE BIT 3 BIT 4 BIT 5
tMCLDV BIT 6 BIT 7 BIT 8
5-3581
Figure 6. T7504 Transmit and Receive Timing, FSEP = 1 MCLK
TIME SLOT tMCHMCL1 1 MCLK tFSHMCL tFSLMCL FSXN tSPHMCL FSEP tSPLMCL 2 3 4 5 6 7 8
tDVMCL DR BIT 1 BIT 2 DR STABLE BIT 3 BIT 4 BIT 5
tMCLDV BIT 6 BIT 7 BIT 8
5-3582
Figure 7. T7504 Receive Timing, FSEP > 1 MCLK 12 Lucent Technologies Inc.
Data Sheet March 1999
T7504 and T5504 Quad PCM Codecs with Filters
Timing Characteristics (continued)
TIME SLOT tMCHMCL1 MCLK tMCLFSH tFSHMCL FSxN tMCH1MCH2 2 3 tFSLMCL 4 5 tMCL2MCL1 6 tFSLMCL 7 8 1
1
FSHFSL tFSHDV Dx tMCLSPH FSEP BIT 1 tMCHDV1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 tMCHDZ BIT 7 BIT 8
tDVMCL DR BIT 1 BIT 2 DR STABLE BIT 3 BIT 4 BIT 5
tMCLDV BIT 6 BIT 7 BIT 8
5-3581.a
Figure 8. T5504 Transmit and Receive Timing, FSEP = 1 MCLK
TIME SLOT tMCHMCL1 1 MCLK tFSHMCL tFSLMCL FSXN tSPHMCL FSEP tDVMCL DR
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5
2
3
4
5
6
7
8
tSPLMCL
tMCLDV
BIT 6 BIT 7 BIT 8
DR STABLE
5-3582.a
Figure 9. T5504 Receive Timing, FSEP > 1 MCLK
Lucent Technologies Inc.
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T7504 and T5504 Quad PCM Codecs with Filters
Data Sheet March 1999
Timing Characteristics (continued)
TIME SLOTS FSX0 FSX1 FSX2 FSX3
19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FSEP
DX
X0
X1
X3
X2
DR
R2
R0
R1
R3 5-3583.a
Figure 10. Typical Frame Sync Timing (2 MHz Operation)
Applications
RF GSXn ZT2 VTR 0.1 F VFXINn
SLIC
0.1 F ACIN RG
ZT1 ZRCV
ZHB
T7504 T5504
VFROn
5-3584
Figure 11. Typical T7504 and T5504/SLIC Interconnection
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Lucent Technologies Inc.
Data Sheet March 1999
T7504 and T5504 Quad PCM Codecs with Filters
Outline Diagrams
28-Pin PLCC
Controlling dimensions are in inches.
12.446 0.127 11.506 0.076 PIN #1 IDENTIFIER ZONE
4 1 26
5
25
11.506 0.076 12.446 0.127
11
19
12
18
4.572 MAX SEATING PLANE 0.10
1.27 TYP
0.51 MIN TYP 0.330/0.533
5-2608r05(F)
Lucent Technologies Inc.
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T7504 and T5504 Quad PCM Codecs with Filters
Data Sheet March 1999
Outline Diagrams (continued)
44-Pin MQFP
Controlling dimensions are in inches.
13.20 0.20 10.00 0.20 PIN #1 IDENTIFIER ZONE
44 34
1
33
13.20 0.20 10.00 0.20
11
23
12
22
DETAIL A
DETAIL B
1.95/2.10 2.35 MAX
SEATING PLANE 0.10
0.80 TYP
0.25 MAX
1.60 REF
0.25 GAGE PLANE SEATING PLANE 0.73/1.03 0.30/0.45
0.130/0.230
0.20
M
DETAIL A
DETAIL B
5-2111r12(F)
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Lucent Technologies Inc.
Data Sheet March 1999
T7504 and T5504 Quad PCM Codecs with Filters
Ordering Information
Device Code T - 7504 - - - ML T - 7504 - - - JL-DB T - 7504 - - - ML-TR T - 5504 - - - ML T - 5504 - - - ML-TR Package 28-Pin, PLCC 44-Pin, MQFP Dry Pack Tray 28-Pin, PLCC Tape & Reel 28-Pin, PLCC 28-Pin, PLCC Tape & Reel Temperature -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C Timing Mode Delayed Delayed Delayed Nondelayed Nondelayed Comcode 107203184 107740466 107231680 107364044 107364051
Lucent Technologies Inc.
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For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Copyright (c) 1999 Lucent Technologies Inc. All Rights Reserved
March 1999 DS99-201ALC (Replaces DS99-184ALC)

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